The present invention relates to semiconductor integrated circuits, and more particularly to integrated circuits including dynamic random access memories (“DRAMs”) having multiple ports and which incorporate trench capacitors.
In integrated circuit memories such as static random access memories (“SRAMs”) and DRAMs, each storage cell or “memory cell” traditionally has only a single port for providing read and write access to a data bit stored therein. However, some types SRAMs and DRAMs have memory cells which include multiple ports per memory cell for providing simultaneous read and/or write access. For example, in a dual port DRAM, a data bit can be simultaneously read from two separate memory cells or written to two separate memory cells that belong to the same column of memory cells in the DRAM. In addition, a data bit can be simultaneously read from one memory cell of the column and written to a separate memory cell of the same column.
In a particular example, commonly assigned U.S. Pat. No. 6,504,204 to Hsu et al. describes a dual port DRAM. Each memory cell of the dual port DRAM is accessible simultaneously through each of two bitlines and through each of two wordlines. The dual port DRAM enables performance gains over DRAMs having traditional single port memory cells because data bits can be read simultaneously from different cells along the same column of memory cells. Thus, the DRAM can be read from one memory cell of a column through a first bitline and simultaneously written to another memory cell of the same column through a second bitline. In addition, when both of the bitlines of a column are used to access the same memory cell, faster reading or writing can be performed because of the greater current carried by the two bitlines than one bitline.
However, further improvements in the structure and performance of a dual port DRAM are possible.